In a case of forming a MOSFET using an SOI substrate in which a single crystal semiconductor layer (silicon layer) is formed on a semiconductor supporting substrate via an insulating film (mainly an oxide film), the insulating film is formed under the source region and the drain region of the MOSFET, whereby it is possible to reduce the parasitic capacity comparing to a case where a MOSFET is formed using a typical bulk substrate. As such, manufacturing an LSI with a use of an SOI substrate is advantageous for a speedup of the element, so that this method has been widely adopted.
In general, MOSFETs using SOI substrates may be of a full depletion type in which an SOI layer below the gate is fully depleted to be operated, or a partial depletion type in which an SOI layer is not fully depleted but is operated with a neutral region still remaining. Although a FET of the partial depletion type has an advantage that it can be manufactured using a forming method according to a process using a bulk substrate, there remains a neutral region which is electrically separated from the substrate. Thereby, a so-called substrate floating effect arises, in which the potential of the neutral region changes corresponding to the operational conditions and the operational current fluctuates. This makes a circuit design difficult. On the other hand, in a FET of the full depletion type, the potential below the channel does not fluctuate since there is no neutral region. Therefore, it has the advantage that a stable circuit operation can be achieved.
However, transistors of the full depletion type are subject to a characteristic deterioration caused by a punch through and a short channel effect, compared to transistors of the partially depleted type. In order to counter this defect, the film thickness of the SOI layer must be made thinner. Generally, in order to keep the fully depleted operation, it is known that the film thickness of the SOI layer must be a ¼ length of the gate length or less. Therefore, if the gate length is 0.1 micron, the film thickness of the SOI layer must be 25 nm or less. However, if the film thickness of the SOI layer becomes thinner, the film thickness of the source/drain regions of the transistor becomes thinner, so that the resistance between the source/drain regions increases. In particular, if a metal silicide layer is formed on the source/drain region, the whole film thickness of the silicon layer is silicified, which causes a problem that an aggregation of silicide and breaking of wire may easily occur, whereby the parasitic resistance increases. Through our researches, we recognized that this phenomenon occurs remarkably if the film thickness of the SOI layer is 30 nm or less. In order to prevent the parasitic resistance increase, it is effective to locally thicken the silicon layer of the source/drain region. To cope with this, a method to raise a silicon layer on the source/drain region by the selective epitaxial growth has been proposed (for example, Japanese Patent Application Laid-open No. 2000-223713). This conventional art will be explained below with reference to drawings.
FIGS. 12(a) through 12(d) are sectional views showing the step of the manufacturing method, in order, of the aforementioned conventional example. There is provided an SOI substrate in which a semiconductor layer 3 is formed on a supporting substrate 1 made of silicon, via a buried insulating film 2 consisting of an oxide film. As shown in FIG. 12(a), the semiconductor layer 3 serving as an active region is isolated by element-isolation insulating films 7c, then a gate insulating film 4 is formed on the semiconductor layer 3, and a mask insulating film 9 consisting of a polycrystalline silicon film and a silicon nitride film is deposited thereon, then by patterning these, a gate electrode 22 is formed. Thereafter, sidewall insulating films 10 are formed on the side surfaces of the gate electrode 22 having the mask insulating film 9.
Next, as shown in FIG. 12(b), single crystal silicon is raised to have, for example, a film thickness of 50 nm under the silicon growth CVD conditions including HCI, to thereby form elevated layers 11e, 11f. Then, by implanting into the semiconductor layer 3, using the ion implanting method, impurity atoms of a conductive type opposite to that of the semiconductor layer serving as a channel region, source/drain regions 3a, 3b are formed.
Next, as shown in FIG. 12(c), after the mask insulation film 9 is removed, cobalt, for example, is deposited on the whole surface by spattering to have a film thickness of 30 nm to 100 nm, and a heat treatment is performed to thereby form cobalt silicide layers 13a, 13b and 13c. Then, the extra cobalt silicide layer is etched away, but with the cobalt silicide layers 13a, 13b and 13c remaining.
Then, as shown in FIG. 12(d), an interlayer insulating film 14 consisting of an oxide film or the like is deposited on the cobalt silicide layers 13a, 13b and 13c by the CVD. Here, the surface of the interlayer insulating film 14 may be flattened by the chemical-mechanical polishing (CMP). Then, contact openings 15a, 15b are selectively formed in the interlayer insulating film 14. Then, a metal such as A1 is deposited by spattering, and is patterned by the photolithography to thereby form a metal electrode 16 contacting the cobalt silicide layers 13a, 13b and 13c via the contact openings 15a, 15b. 
In a method of forming the elevated layers using the aforementioned selective epitaxial growth method, facets are generated at the growth edges of the elevated layers, which causes the width of the growth edges to narrow. As such, it is difficult to form elevated layers with low resistance. Further, the selective epitaxial growth needs a special CVD device suitable for the method, which causes the manufacturing cost to increase.
Further, in a case that silicon is raised under the condition that the facets are not formed at the growth edges of the elevated layers, selectivity is degraded, whereby a special lithography process is required to prevent a short circuit. As a method of forming the elevated layers in which selective growth is not performed and the lithography process is not required, there is proposed a method in which element-isolation insulating films are so formed as to be taller than the semiconductor layer (SOI layer), and by using CVD, CMP and the like, a conductive material such as silicon is buried into a depression defined by the gate electrode and the element-isolation insulating films.
In this case, however, the surface height of the gate electrode and the surface height of the elevated layer coincide with each other, which causes a problem that a short circuit tends to occur when a silicide layer is formed.
It is an object of the present invention to solve the aforementioned problems in the conventional art, which object includes, first, to enable elevated layers with low resistance to be formed to thereby reduce the parasitic resistance in source/drain regions, and secondly, to enable elevated layers which are less possible to cause a short circuit to be formed without using a lithography process.